1. Technical Field
The present invention relates to damascene interconnect structures and methods for fabricating them, and particularly to a method for fabricating a damascene interconnect structure that has air gaps between metal lines.
2. Description of Related Art
In semiconductor devices, such as large scale integrated circuits (LSI) and ultra-large scale integration (ULSI) integrated circuits, the damascene process has been commonly used to form interconnect lines. A typical damascene process involves etching trenches or canals in a planar dielectric layer, and then filling the trenches or canals with metal, such as aluminum or copper. After filling, the excess metal outside the trenches is planarized and polished by chemical polishing so that metal is only left within the trenches.
FIG. 8 is a cross-sectional view of a typical damascene interconnect structure. The damascene interconnect structure 1 includes a substrate 10, a dielectric layer 11 formed on the substrate 10, a plurality of trenches 15 formed in the dielectric layer 11, a plurality of metal lines 17 filled in the trenches 15, and a capping layer 19 covering the dielectric layer 11 and the metal lines 17.
A method for fabricating the damascene interconnect structure 1 is as follows. In step 1, referring to FIG. 9, a substrate 10 is provided, and a dielectric film 110 and a photoresist layer (not shown) are sequentially formed on the substrate 10. Then, the photoresist layer is formed into a patterned photoresist layer 13 by an exposure and developing process.
In step 2, referring to FIG. 10, by using the patterned photoresist layer 13 as a mask, the dielectric film 110 is etched to form a plurality of trenches 15. Thereby, remaining portions of the dielectric film 110 define a dielectric layer 11.
In step 3, referring to FIG. 11, a metal layer 170 is deposited on the dielectric layer 11 and is completely filled in the trenches 15.
In step 4, referring to FIG. 12, the metal layer 170 is polished with a chemical mechanical polishing (CMP) process. Thereby, excess portions of the metal layer 170 covering the dielectric wall 11 are removed, and only portions of the metal in the trenches 15 remain. These remaining portions form a plurality of metal lines 17. Then a capping layer 19 is deposited on the dielectric layer 11 and the metal lines 17, so as to form the damascene interconnect structure 1.
In order that the damascene interconnect structure 1 has good electrical properties, a resistance R in the metal lines 17 and a capacitance C between the metal lines 17 must both be as low as possible. This is so that the resistance-capacitance (RC) delay and leakage current caused by the resistance R and the capacitance C can be minimal.
With recent developments in semiconductor technology, millions and even billions of electronic elements can be integrated in one chip. Current flows and electrical processing occurring in a single chip are massive. Therefore leakage current and RC delay can be prevalent, and may significantly impair the performance of the chip.
What is needed is a damascene interconnect structure and a method for fabricating the same which can help ensure that performance of a corresponding integrated circuit is satisfactory.